1. Field of Invention
The present invention relates to a memory device. More particularly, the present invention relates to a flash memory structure and operating method thereof.
2. Description of Related Art
Flash memory is a device having multiple data access, read-out and erase capability. Furthermore, data stored within a flash memory will be retained even after power to the device is cut off. Hence, flash memory has become one of the most popular non-volatile memories deployed inside personal computers and electronic equipment.
A typical flash memory device has a floating gate and a control gate fabricated using doped polysilicon. The control gate is set up over the floating gate with the two layers separated from each other by a dielectric layer. The floating gate is isolated from an underlying substrate by a tunneling oxide layer, thereby forming a stack gate flash memory structure.
To write data into the flash memory, a bias voltage is applied to the control gate and the source/drain region and hence electrons are injected into the floating gate. To read data from the flash memory, an operating voltage is applied to the control gate. With the charging condition inside the floating gate affecting the conductive state of the channel, a value of xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d can be determined. To erase data from the flash memory, relative potential of the substrate, the drain (source) region or the control gate is raised. Through action caused by a tunneling effect, trapped electrons inside the floating gate penetrate through the tunneling oxide layer into the substrate or the drain (source) terminal (the so-called substrate erase or drain (source) side erase) or penetrate through the dielectric layer into the control gate.
However, the quantity of electrons bled out from the floating gate is difficult to control in an operation to erase data from the flash memory. If an excessive amount of electrons flows out of the floating gate, the floating gate will contain a net positive charge leading to an over-erase condition. If such over-erase phenomena is severe, the channel underneath the floating gate may conduct without the application of an operating voltage resulting in erroneous reading. To reduce the over-erasing problem, most flash memory has a split-gate design. One major aspect of a split-gate design is the addition of a select gate (or erase gate) on the sidewall of the control gate and the floating gate and above the substrate besides the control gate and the floating gate. The selective gate (or erase gate) is isolated from the control gate, the floating gate and the substrate through a gate dielectric layer. When over-erase is severe so that the channel underneath the floating gate is conductive even without applying an operating voltage to the control gate, the channel underneath the select gate still remains shut. In other words, the source/drain region is non-conductive and erroneous reading from the flash memory is prevented. Nevertheless, a split-gate structure demands a larger area and hence each memory cell has a larger dimension compared with a conventional stack gate flash memory. That means, overall level of integration has to be reduced. To reduce the size of each memory cell, a dual-cell flash memory structure with two cells using the same select gate is invented.
FIG. 1 is a schematic cross-sectional view of a conventional dual-cell flash memory structure. The dual-cell flash memory structure in FIG. 1 includes a first memory cell 101a and a second memory cell 101b over a substrate 100. The first memory cell 101a has a gate structure 102a that includes a tunneling oxide layer 104a, a floating gate 106a, a gate dielectric layer 108a, a control gate 110a and a cap layer 112a. Similarly, the second memory cell 101b has a gate that includes a tunneling oxide layer 104b, a floating gate 106b, a gate dielectric layer 108b, a control gate 110b and a cap layer 112b. Spacers 114a and 114b are attached to the sidewalls of the first gate structure 102a and the second gate structure 102b respectively. Source/drain regions 116a and 116b are located in the substrate 100 on opposite sides of the first gate structure 102a and the second gate structure 102b. A select gate 118 not only covers the gate structures 102a, 102b but also extends from one source/drain region 116a to another source/drain region 116b. 
To program data into the memory cell 101a of the dual-cell flash memory structure, the memory cell 101b serves as a channel transistor. A bias voltage of 10V is applied to the control gate 110a; a bias voltage of 10V is applied to the control gate 110b so that the channel underneath the memory cell 101b is opened; a bias voltage of 2V is applied to the select gate 118; a bias voltage of 2V is applied to the source/drain region 116a and a bias voltage of 0V is applied to the source/drain region 116b. With this voltage setup, electrons moving from the source/drain region 116b towards the source/drain region 116a are accelerated by the Intense electric field close to the source/drain region 116a to generate hot electrons. Kinetic energy of these electrons overcomes the energy barrier in the tunneling oxide layer 104a, and together with the high positive bias voltage applied to the control gate 110a, the hot electrons are injected into the floating gate 106a from the source/drain region 116a. Hence, the memory cell 101a is programmed. Similarly, to program data into the memory cell 101b of the dual-cell flash memory structure, the memory cell 101aserves as a channel transistor. A bias voltage of 10V is applied to the control gate 110b; a bias voltage of 10V is applied to the control gate 110a so that the channel underneath the memory cell 110a is opened; a bias voltage of 2V is applied to the select gate 118; a bias voltage of 2V is applied to the source/drain region 116b and a bias voltage of 0V is applied to the source/drain region 116a. With this voltage setup, electrons moving from the source/drain region 116a towards the source/drain region 116b are accelerated by the intense electric field close to the source/drain region 116b to generate hot electrons. Kinetic energy of these electrons overcomes the energy barrier in the tunneling oxide layer 104b, and together with the high positive bias voltage applied to the control gate 110b. the hot electrons are injected into the floating gate 106b from the source/drain region 116b. Hence the memory cell 101b is programmed.
In the aforementioned method of programming a dual-cell flash memory structure, if the memory cell 101b is programmed immediately after programming the memory cell 101a, the memory cell 101b may be affected by the programmed memory cell 101a leading to a lowering of programming current. Hence, programming speed of the memory cell 101b will be lower than the memory cell 101a. In other words, the dual-cell flash memory will have an unsymmetrical programming operation resulting In a slower overall operating speed.
Accordingly, one object of the present invention is to provide a flash memory structure and an operating method thereof for increasing the level of integration of the memory device.
A second object of this invention is to provide a flash memory structure and an operating method thereof for eliminating unsymmetrical programming in memory cells so that memory cell current can be reduced and overall operating speed of the memory device can be increased.
A third object of this invention is to provide a flash memory structure and an operating method that can prevent over-erasing memory cells.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a flash memory device structure. The flash memory device structure includes a first conductive type substrate, a second conductive type first well a first conductive type second well, a pair of gate structures, a select gate and a pair of first conductive type source/drain regions. The second conductive type first well is located within the first conductive type substrate. The first conductive type second well is located within the second conductive type first well. The pair of gate structures is positioned over the first conductive type substrate. The select gate is positioned between the pair of gate structures. The pair of first conductive type source/drain regions is located within the first conductive type second well on the opposite side of the respective gate structures.
Each gate structure has a floating gate, a tunneling oxide layer, a control gate, a gate dielectric layer, a first spacer and a second spacer. The floating gate is set up over the first conductive type substrate. The tunneling oxide layer is set up between the floating gate and the first conductive type substrate. The control gate is set up over the floating gate. The gate dielectric layer is set up between the control gate and the floating gate. The first spacer is set up on the sidewalls and upper surface of the control gate. The second spacer is set up on the sidewalls of the floating gate. The tunneling oxide layer may extend into the gap between the select gate and the first conductive type substrate.
Since two neighboring gate structures (memory cells) uses a single select gate in this invention corresponding level of integration for the flash memory devices is increased.
This invention also provides a method of operating a flash memory device. The flash memory device includes a P-type substrate, a deep N-well, a P-well, a first memory cell, a second memory cell, a select gate, a first source/drain region and a second source/drain region. The deep N-well is embedded within the P-type substrate. The P-well is embedded within the deep N-well. The first memory cell and the second memory cell are set up over the P-type substrate. The first memory cell has a first control gate and the second memory cell has a second control gate. The select gate is set up between the first memory cell and the second memory cell. The first source/drain region and the second source/drain region are set up in the P-well on the opposite side of the first memory cell and the second memory cell. Both the first source/drain region and the second source/drain region are N-type conductive layers. To program the first memory cell of the flash memory device, a first positive voltage is applied to the first control gate and a first negative voltage is applied to the P-well so that the select gate is at a ground potential and the first source/drain region and the second source/drain region are in a floating state. Through the voltage setup, the first memory cell is programmed via the F-N tunneling effect. To read data from the first memory cell of the flash memory device, a second positive voltage is applied to the select gate and the first control gate, a third positive voltage is applied to the second control gate, a fourth positive voltage is applied to the second source/drain region and a ground voltage is applied to the first source/drain region and the P-well. To erase data from the memory cells on the same word line,a fifth positive voltage is applied to the select gate, zero voltage is applied to the first control gate and the second control gate, the first source/drain region and the second source/drain region is set to a floating state so that F-N effect is able to wipe out the data on an entire page of flash memory devices.
The aforementioned method of operating the flash memory device may further include applying a first positive voltage to the second control gate and a first negative voltage to the P-well when the second memory cell in the flash memory device is programmed. Hence, the select gate is at a ground potential and both the first source/drain region and the second source/drain region remain in a floating state so that the second memory cell is again programmed through the F-N tunneling effect.
In the flash memory device of this invention, an isolating P-well Is formed inside the deep N-well. By applying a suitable voltage to the control gate and the isolated P-well, F-N tunneling effect can be utilized to force electrons in the substrate (the isolated P-well) through the tunneling oxide layer into the floating gate. Thus, there is very little effect on the programming of data into the second memory cell immediately after programming data into the first memory cell. In other words, unsymmetrical programming problem in the memory cells is prevented.
In addition, the F-N tunneling effect is utilized to program the channel flash memory device. Since F-N tunneling has very high electron injection efficiency, memory cell current required for programming can be reduced and operating speed can be increased. Furthermore, both programming and erasing are carried out using the F-N tunneling effect, which consumes very little current. Therefore, overall power consumption of the memory device is reduced. Moreover, the method can also be applied to program/erase the data in parallel on a large page.
It Is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.